The Micron GDDR6X memory brings a lot of new stuff to the table. It is faster, doubles the I/O data rate, and is the first to implement PAM4 multi-level signaling in memory dies. With the Geforce RTX 3090 class products, Micron’s GDDR6X memory achieves a bandwidth of up to 1 TB/s which is used to power next-generation gaming experiences at high-fidelity resolutions such as 8K.
Micron GDDR6X graphics memory doubles input/output (I/O) performance while minimizing the cost of memory. Working with AI-innovation leader NVIDIA, Micron delivers higher bandwidth by enabling multi-level signaling in the form of four-level pulse amplitude modulation (PAM4) technology in this memory device via Micron
The new GDDR6X SGRAM:
Doubles the data rate of SGRAM at a lower power per transaction while enabling the breaking of the 1 Terabyte per second (TB/s) system memory bandwidth boundary for graphics card applications;
Is the first discrete graphics memory device that employs PAM4-encoded signaling between the processor and the DRAM, using four voltage levels to encode and transfer two bits of data per interface clock.
Can be designed and operated stably at high speeds and built-in mass-production.
As mentioned, GDDR6X features the brand new PAM4 multilevel signaling techniques, which help transfer data much faster, double the I/O rate, pushing the capability of each memory dies from 64 GB/s to 84 GB/s. The Micron GDDR6X memory dies are also the only graphics DRAM that can be mass-produced while featuring PAM4 signaling.
What is interesting is that Micron quotes that its GDDR6X memory can hit speeds of up to 22.4 Gbps whereas we have only got to see 21 Gbps in action on the GeForce RTX 3090 Ti. It is likely that AIBs could utilize higher binned dies as they are available. Micron does has faster chips but those aren’t coming to NV 40 series graphics cards for now.
It’s not just faster speeds but Micron’s GDDR6X provides higher bandwidth while sipping in 15% lower power per transferred bit compared to the previous generation GDDR6 memory. PAM4 signaling is a big upgrade from the two-level NRZ signaling on the GDDR6 memory.
Instead of transmitting two binary bits of data each clock cycle (one bit on the rising edge and one bit on the falling edge of the clock), PAM4 sends two bits on each clock edge, encoded using four different voltage levels. The voltage levels are divided into 250 mV steps with each level representing two bits of data – 00, 01, 10, or 11 sent on each clock edge (still DDR technology).
Micron GDDR6X Memory
FeatureGDDR5GDDR5XGDDR6GDDR6X
DensityFrom 512Mb to 8Gb8Gb8Gb, 16Gb8Gb, 16Gb
VDD and VDDQEither 1.5V or 1.35V1.35VEither 1.35V or 1.25VEither 1.35V or 1.25V
VPPN/A1.8V1.8V1.8V
Data ratesUp to 8 Gb/sUp to 12Gb/sUp to 16 Gb/s19 Gb/s, 21 Gb/s,
>21 Gb/s
Channel count1122
Access granularity32 bytes64 bytes
2x 32 bytes in pseudo 32B mode2 ch x 32 bytes2 ch x 32 bytes
Burst length816 / 8168 in PAM4 mode
16 in RDQS mode
SignalingPOD15/POD135POD135POD135/POD125PAM4 POD135/POD125
PackageBGA-170
14mm x 12mm 0.8mm ball pitchBGA-190
14mm x 12mm 0.65mm ball pitchBGA-180
14mm x 12mm 0.75mm ball pitchBGA-180
14mm x 12mm 0.75mm ball pitch
I/O widthx32/x16x32/x162 ch x16/x82 ch x16/x8
Signal count61
– 40 DQ, DBI, EDC
– 15 CA
– 6 CK, WCK61
– 40 DQ, DBI, EDC
– 15 CA
– 6 CK, WCK70 or 74
– 40 DQ, DBI, EDC
– 24 CA
– 6 or 10 CK, WCK70 or 74
– 40 DQ, DBI, EDC
– 24 CA
– 6 or 10 CK, WCK
PLL, DCCPLLPLLPLL, DCCDCC
CRCCRC-8CRC-82x CRC-82x CRC-8
VREFDExternal or internal per 2 bytesInternal per byteInternal per pinInternal per pin
3 sub-receivers per pin
EqualizationN/ARX/TXRX/TXRX/TX
VREFCExternalExternal or InternalExternal or InternalExternal or Internal
Self refresh (SRF)Yes
Temp. Controlled SRFYes
Temp. Controlled SRF Hibernate SRFYes
Temp. Controlled SRF Hibernate SRF
VDDQ-offYes
Temp. Controlled SRF Hibernate SRF
VDDQ-off
ScanSENIEEE 1149.1 (JTAG)IEEE 1149.1 (JTAG)IEEE 1149.1 (JTAG)
