AMD EPYC 9004 “Genoa”, the 4th Gen Data Center CPU lineup, featuring the latest Zen 4 core architecture has officially made its debut today. Featuring an impressive core count and powered on the latest SP5 platform, this is one server ecosystem that others shouldn’t mess with!
AMD EPYC 9004 “Genoa Zen 4” Data Center CPUs Official: Zen 4 Powers The Fastest Server CPUs On The Planet With Up To 96 Cores & 192 Threads
The AMD EPYC 9004 Genoa family is the start of a new server ecosystem for the EPYC brand. It covers multiple segments, multiple families, and multiple families.
The AMD Zen 4 lineup for Data Centers will be split into three families, the standard Zen 4 for EPYC Genoa, the Compute Density-Optimized Zen 4C for EPYC Bergamo, and the Cache-Optimized Zen 4 V-Cache within the EPYC Genoa-X series. Furthermore, the lineup will be featuring a cost-optimized and entry-level server offering known as EPYC Siena which will feature the same Zen 4 cores but on an entirely new platform known as SP6 which will once again focus on optimizing TCO compared to SP5. The lineup will be branded under the EPYC 8004 family.
AMD EPYC 9004 “Genoa Zen 4” Server CPU Lineup
The AMD EPYC 9004 Genoa “Zen 4” CPUs are based on a 5nm Chiplet architecture which we have seen on the Ryzen 7000 and Radeon 7000 products. The CPU delivers a 14% increase in IPC, a 1% increase over the consumer Zen 4 parts. The reason for the slight uplift is the geomean data which is taken across a larger set of workloads compared to consumer-centric workloads for the Ryzen chips.
The standard Zen 4 lineup will feature up to 12 CCDs, 96 cores, and 192 threads. Each CCD will come with 32 MB of L3 cache and 1 MB of L2 cache per core. The EPYC 9004 CPUs will pack the latest instructions such as BFLOAT16, VNNU, AVX-512 (256b data path), addressable memory of 57b/52b, and an updated IOD with an internal AMD Gen3 Infinity Fabric architecture with higher bandwidth (die-to-die interconnect).
The AMD EPYC 9004 “Genoa” CPU is split into six SKU segments which include:
Density Optimized
Cache Optimized
Frequency Optimized
Cost Optimized
Density + Frequency
Balanced
The top parts are based on a 12 CCD SKU with up to 96 cores, 192 threads, and 384 MB of L3 cache. These SKUs will range between 360W-400W TDPs. Next up, we have the 8 CCD SKUs which feature a total of 16 SKUs that range from 16 cores up to 64 cores. These chips pack 256 MB of L3 cache & TDPs that range between 280/320/360W. Lastly, we have the 4 CCD SKUs which include 4 SKUs that offer 16-32 cores. These chips will offer 64 to 128 MB of L3 cache and TDPs in the range of 200-210 Watts. As for frequencies, the EPYC 9004 “F” SKUs will have a boost target range above 4.0 GHz and the rest of the chips are rated at 3.7 GHz (boost).
Compared to EPYC Milan, the AMD Zen 4 CCD is 11% smaller than the Zen 3 CCD (80mm vs 72mm). The IOD is also 5% smaller (416mm vs 397mm). The package and socket size has increased a lot & that is mainly due to the fact that EPYC Genoa chips incorporate 50% more CCDs than EPYC Milan chips (12 vs 8 CCDs). The Genoa package measures 5428mm2 while the socket has a total area of 6080 mm2 while SP3 measures 4410mm2. Do note how the number of pins comes close to the area size of each respective socket.
AMD SP5 “LGA 6096” Server CPU Platform
The LGA 6096 socket will feature 6096 pins arranged in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket. We have already listed the size and dimensions of this socket above so let’s talk about its power ratings. It looks like the peak power of the LGA 6096 SP5 socket will be rated at up to 700W which will only last for 1ms, the peak power at 10ms is rated at 440W while the peak power with PCC is rated at 600W. If the cTDP is exceeded, then the EPYC chips featured on the SP5 socket will return to these limits within 30ms.
AMD’s EPYC Genoa CPUs will feature 128 PCIe Gen 5.0 lanes of which 112 PCIe Gen 5 lanes will be available since the remaining 16 are reserved, 160 for a 2P (dual-socket) configuration. The SP5 platform will also feature DDR5-5200 memory support which is an insane improvement over the existing DDR4-3200 Mbps DIMMs. But that’s not all, it will also support up to 12 DDR5 memory channels and 2 DIMMs per channel which will allow up to 12 TB of system memory using 1 TB 3DS RDIMM modules.
The platform will feature support for 12 DDR5 channels with up to 4800 Mbps DIMM support and include options for 2,4,6,8,10,12 interleaving. Both RDIMM & 3DS RDIMM will be supported with 2 DIMMs per channel for up to 6 TB/ capacities per socket (using 256 GB 3DS RDIMMs). There will be 160 gen 5 lanes available on the 2P platform, 12 PCIe Gen 3 lanes (8 lanes on 1P), 32 SATA lanes, & 64 IO lanes supporting CXL 1.1+ with bifurcations down to x4 and SDCI (Smart Data Cache Injection).
AMD EPYC Milan Zen 3 vs EPYC Genoa Zen 4 Size Comparisons:
CPU NameAMD EPYC MilanAMD EPYC Genoa
Process NodeTSMC 7nmTSMC 5nm
Core ArchitectureZen 3Zen 4
Zen CCD Die Size80mm272mm2
Zen IOD Die Size416mm2397mm2
Substrate (Package) AreaTBD5428mm2
Socket Area4410mm26080mm2
Socket NameLGA 4094LGA 6096
Max Socket TDP450W700W
AMD EPYC 9004 “Genoa Zen 4” Server CPU Performance
In terms of performance, the charts showcase the SPEC2017 Integer (Base) benchmarks for 14 chips within the AMD EPYC Genoa lineup. At least five of the chips sit above 1000 points while the rest are positioned competitively in the mid-tier and entry-tier segments. All benchmarks were done on a 2P (dual-socket) platform so two chips are used.
AMD EPYC Genoa SPECrate 2017 Integer_Base Benchmark (All 2P/2S)
AMD EPYC Genoa SPECrate 2017 Integer_Base (2P)
In terms of energy efficiency, AMD has touted a 2.6x leap over Intel’s 3rd Gen Xeon Platinum (Ice Lake-SP) platform within the 2P Integer (performance per watt) score on SPECrate 2017. Following is the score breakdown:
AMD EPYC Genoa SPECrate 2017 Int_energy_base Benchmark (2P)
AMD EPYC 9004 “Genoa Zen 4” Server CPU SKUs:
CPU NameArchitectureFamilyTotal CCDsCores / ThreadsL3 CacheBase / Max ClocksTDPCPU Positioning
EPYC 96645nm Zen 4Genoa1296/192384 MB2.25-3.80 GHz400W (320-400W)Density Optimized
EPYC 9654P5nm Zen 4Genoa1296/192384 MB2.05 -3.70 GHz360W (320-400W)Density Optimized (Single-Socket)
EPYC 96545nm Zen 4Genoa1296/192384 MB2.05 – 3.70 GHz360W (320-400W)Density Optimized
EPYC 96345nm Zen 4Genoa1284/168384 MB2.00-3.70 GHz290W (320-400W)Density Optimized
EPYC 9554P5nm Zen 4Genoa864/128256 MB2.70-3.70 GHz360W (320-400W)Density + Frequency
EPYC 95545nm Zen 4Genoa864/128256 MB2.70-3.70 GHz360W (320-400W)Density + Frequency
EPYC 95345nm Zen 4Genoa864/128256 MB2.30 – 3.70 GHz280W (240-280W)Balanced
EPYC 9454P5nm Zen 4Genoa848/96256 MB2.25 – 3.70 GHz280W (240-280W)Balanced
EPYC 94545nm Zen 4Genoa848/96256 MB2.25 – 3.70 GHz280W (240-280W)Balanced
EPYC 9354P5nm Zen 4Genoa832/64256 MB2.75-3.70 GHz280W (240-280W)Core Strength
EPYC 93545nm Zen 4Genoa832/64256 MB2.75-3.70 GHz280W (240-280W)Core Strength
EPYC 93345nm Zen 4Genoa432/64128 MB2.50-3.70 GHz210W (200-240W)Balanced
EPYC 92545nm Zen 4Genoa424/48128 MB2.40-3.70 GHz200W (200-240W)Balanced
EPYC 92245nm Zen 4Genoa424/4864 MB2.15-3.70 GHz200W (200-240W)Cost Optimized
EPYC 91245nm Zen 4Genoa416/3264 MB2.60-3.70 GHz200W (200-240W)Cost Optimized
EPYC 9474F5nm Zen 4Genoa848/96256 MB3.60-4.00 GHz+360W (320-400W)Frequency Optimized
EPYC 9374F5nm Zen 4Genoa832/64256 MB3.40-4.00 GHz+320W (320-400W)Frequency Optimized
EPYC 9274F5nm Zen 4Genoa824/48256 MB3.30-4.00 GHz+320W (320-400W)Frequency Optimized
EPYC 9174F5nm Zen 4Genoa816/32256 MB3.20-4.00 GHz+320W (320-400W)Frequency Optimized
The post AMD 4th Gen EPYC 9004 “Genoa Zen 4” CPUs Launched: Up To 96 Cores, 192 Threads, 384 MB L3 Cache & Crushing All Other Server Chips by Hassan Mujtaba appeared first on Wccftech.
