Micron is announcing the commencement of volume shipments for its new DDR5-4800 SDRAM for AMD’s 4th Gen EPYC Genoa “Zen 4” CPUs.
Micron DDR5 Memory Now Supporting 4th Gen AMD EPYC Genoa CPUs, Based on “Zen 4” Architecture
Press Release: Micron Technology, Inc., (Nasdaq: MU) today announced it is volume shipping DDR5 SDRAM memory for the data center that is validated for new AMD EPYC 9004 Series processors.
Micron’s new DDR5 SDRAM delivers a 1.5 times increase in data rates at 4800 MT/s when compared to DDR4 3200, and enables features like on-die ECC, Error Check and Scrub (ECS), and fault bounding for increased reliability in the data center while continuing to scale density. Additionally, Micron is providing flexible memory solutions capable of fueling the continued expansion of CPU cores for data-intensive workloads like AI, advanced analytics, and high-performance computing (HPC).
Micron continues to lead the industry transition to DDR5 through our ongoing development and validation collaborations with AMD and our ecosystem partners to ensure readiness for 4th Gen AMD EPYC processors.
Extracting insights from huge volumes of data requires advanced, compute-intensive AI workloads, necessitating more memory bandwidth. DDR5 is the game-changing memory required to enable performance and efficiency in the data center.
Raj Hazra, senior vice president and general manager of Micron’s Compute and Networking Business Unit.
With introductory data rates at 4800 MT/s and other features to improve overall data bus efficiency, Micron DDR5 memory enables a 36% increase in bus efficiency and approximately two times the effective bandwidth when compared to DDR4 3200 to feed the continued growth of CPU cores in the modern data center. Micron will continue development on DDR5 to facilitate data rates up to 8800 MT/s, which would provide three times the effective bandwidth compared to DDR4 3200 as processors and workloads continue to evolve.
4th Gen AMD EPYC processors continue to raise the bar for workload performance in the modern data center while simultaneously delivering exceptional energy efficiency. 4th Gen AMD EPYC processors will transform our customers’ data center operations by accelerating time to value, driving the lower total cost of ownership, and helping enterprises to address their sustainability goals,” said Ram Peddibhotla, corporate vice president, of EPYC product management, AMD.
We internally tested the STREAM memory benchmark and found that Micron DDR5 and the 4th Gen AMD EPYC processor achieved a 2X memory bandwidth performance over Micron DDR4 3rd Gen AMD EPYC processor.
Malcolm Humphrey, vice president, and general manager of Micron’s Core Compute Business.
The requirement for systems that can deliver higher compute capability has never been greater. As modern servers pack more processing cores into CPUs, the memory bandwidth per CPU core has been decreasing. DDR5 memory alleviates this by providing the fastest bandwidth of any generation of DDR. Improving on previous generations, DDR5 offers higher bandwidths and enables increased reliability, availability, and serviceability as well as scaling.
The continued growth of modeling & simulation, and machine learning workloads in HPC and AI means that our customers are demanding memory solutions that maximize effective bandwidth. Our collaboration with Micron throughout the development and validation phase, with these performance-intensive workloads in mind, allows us to deliver next-generation platforms with a new era in memory performance accelerated by DDR5.
Scott Tease, vice president of HPC & AI, Lenovo Infrastructure Solutions Group.
From its inception, Micron has played a pivotal role in JEDEC’s creation of DDR5 memory specifications as a lead developer and was one of the first to sample DDR5 with data center customers. The one-of-a-kind Micron Technology Enablement Program (TEP) gave system designers early access to key internal resources to assist their DDR5 validation and qualification processes. Collaboration efforts continue by working with system enablers to advance DDR5 RAS features, data rates and the overall available feature set.
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