TSMC Roadmap Lays Out Advanced CoWoS Packaging Technologies, Ready For Next-Gen Chiplet Architectures & HBM3 Memory

TSMC has laid out its advanced packaging technology roadmap and showcased its next-gen CoWoS solutions which are ready for next-gen chiplet architectures and memory solutions.

TSMC Lays Out Its Advanced CoWoS Packaging Technology Roadmap, 2023 Design Ready For Chiplet & HBM3 Architectures

The Taiwanese-based semiconductor giant has gained rapid progress in deploying advanced chip packaging technologies in the industry. Within a decade, the company has launched five different generations of CoWoS (Chip-on-Wafer-on-Substrate) packages that are currently deployed or being deployed in consumer and server space.

The company expects to release its Gen 5 CoWoS packaging solution later this year which will push the transistor count by 20x over the 3rd Gen packaging solution. The new package will come with an interposer area increase of 3 times, 8 HBM2e stacks for up to 128 GB capacities, a brand new TSV solution, Thick CU interconnect, and a new TIM (Lid package). The most notable solution that will make use of the Gen 5 packaging technology from TSMC is namely AMD’s MI200 ‘Aldebaran’ GPU.

The AMD Aldebaran GPU will be the first MCM GPU fabricated and produced over at TSMC. The GPU will be powered by AMD’s CDNA 2 architecture and is expected to rock some insane specs such as over 16,000 cores and 128 GB of HBM2E memory. NVIDIA’s Hopper GPU would also be making use of an MCM chiplet architecture and is expected to be produced at TSMC. This GPU is expected to launch in 2022 so we can expect NVIDIA to leverage from the Gen 5 solution too.

By Gen 6, TSMC will have a larger reticle area to integrate more chiplets and more DRAM packages. The package design has not yet been finalized by TSMC expects to house up to 8 HBM3 DRAM and two compute chiplet dies on the same package. TSMC is also going to offer the latest SOC thermal solution in the form of Metal Tim which is expected to decrease the package thermal resistance to 0.15x over Gel TIM used in 1st Gen. This is still far off and will be designed for products that will be manufactured on the N3 process node so we are looking at either CDNA 3 (MI300) or Ampere Next Next.

The post TSMC Roadmap Lays Out Advanced CoWoS Packaging Technologies, Ready For Next-Gen Chiplet Architectures & HBM3 Memory by Hassan Mujtaba appeared first on Wccftech.