AMD launched its first CDNA GPU-based accelerator, the Instinct MI100, last year and the latest reports suggest that its successor, the MI200, could launch this year. The AMD Instinct accelerators feature the CDNA architecture that is designed for compute-intensive and HPC workloads and the 2nd gen of these chips is going to bring a lot of new features and technologies.
AMD Instinct MI200 Reportedly Features CDNA 2 MCM Architecture & Launches In Late 2021
The details were posted by Komachi over at his Twitter feed and from the looks of it, the Instinct MI200 will be replacing the MI100 as the new flagship accelerator for HPC. Based on the naming convention itself, it looks like MI200 will be twice as fast as Instinct MI100 but to achieve this, AMD is expected to go all out with its MCM design.
The Instinct MI200 is expected to be launching alongside AMD’s EPYC Trento chips. The Trento line is going to be a slight variation of the Milan chips for the Supercomputer sector. They are not going to be similar to Genoa as that features the next-gen Zen 4 cores but it should offer a range of new capabilities which we will learn close to launch. As for MI200, it is expected to launch in 2021 but we should expect a late Q4 arrival since MI100 was introduced in a similar timeframe (Q4 2020).
Other than that, the AMD MI200 is listed as an MCM ‘Special FIO Accelerator’ for HPE Cray EX. That could explain where the MI200 name comes from. An MCM (Multi-Chip-Module) design could mean that we could still be looking at a Vega Compute GPU but two of them fused over the same PCB & connected by a next-generation Infinity Fabric interconnect.
AMD Radeon Instinct Accelerators 2020
| Accelerator Name | AMD Radeon Instinct MI6 | AMD Radeon Instinct MI8 | AMD Radeon Instinct MI25 | AMD Radeon Instinct MI50 | AMD Radeon Instinct MI60 | AMD Instinct MI100 | AMD Instinct MI100 |
|---|---|---|---|---|---|---|---|
| GPU Architecture | Polaris 10 | Fiji XT | Vega 10 | Vega 20 | Vega 20 | Arcturus | TBA |
| GPU Process Node | 14nm FinFET | 28nm | 14nm FinFET | 7nm FinFET | 7nm FinFET | 7nm FinFET | Advanced Process Node |
| GPU Cores | 2304 | 4096 | 4096 | 3840 | 4096 | 7680 | 7680 x 2 (MCM) ? |
| GPU Clock Speed | 1237 MHz | 1000 MHz | 1500 MHz | 1725 MHz | 1800 MHz | ~1500 MHz | TBA |
| FP16 Compute | 5.7 TFLOPs | 8.2 TFLOPs | 24.6 TFLOPs | 26.5 TFLOPs | 29.5 TFLOPs | 185 TFLOPs | TBA |
| FP32 Compute | 5.7 TFLOPs | 8.2 TFLOPs | 12.3 TFLOPs | 13.3 TFLOPs | 14.7 TFLOPs | 23.1 TFLOPs | TBA |
| FP64 Compute | 384 GFLOPs | 512 GFLOPs | 768 GFLOPs | 6.6 TFLOPs | 7.4 TFLOPs | 11.5 TFLOPs | TBA |
| VRAM | 16 GB GDDR5 | 4 GB HBM1 | 16 GB HBM2 | 16 GB HBM2 | 32 GB HBM2 | 32 GB HBM2 | TBA |
| Memory Clock | 1750 MHz | 500 MHz | 945 MHz | 1000 MHz | 1000 MHz | 1200 MHz | TBA |
| Memory Bus | 256-bit bus | 4096-bit bus | 2048-bit bus | 4096-bit bus | 4096-bit bus | 4096-bit bus | TBA |
| Memory Bandwidth | 224 GB/s | 512 GB/s | 484 GB/s | 1 TB/s | 1 TB/s | 1.23 TB/s | TBA |
| Form Factor | Single Slot, Full Length | Dual Slot, Half Length | Dual Slot, Full Length | Dual Slot, Full Length | Dual Slot, Full Length | Dual Slot, Full Length | OAM |
| Cooling | Passive Cooling | Passive Cooling | Passive Cooling | Passive Cooling | Passive Cooling | Passive Cooling | Passive Cooling |
| TDP | 150W | 175W | 300W | 300W | 300W | 300W | TBA |
Do note that AMD’s CDNA 2 GPU will be fabricated on a brand new process node & are confirmed to feature a 3rd Generation AMD Infinity architecture that extends to Exascale by allowing up to 8-Way coherent GPU connectivity.
According to Coelacanth’s Dream (via Videocardz), it is reported that the MI200 accelerator will utilize a new variant of the GFX900 GPU architecture (Vega) known as GFX90A which adds support for full-rate FP64 compute capabilities. Once again, the AMD MI200 accelerator sounds like it will go ahead with NVIDIA’s future Lovelace MCM GPUs for HPC market.
The post AMD Instinct MI200 CDNA 2 GPU Powered Accelerator Reportedly Launching In 2021, Could Feature MCM Architecture by Hassan Mujtaba appeared first on Wccftech.
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